1. Field of the Invention
This invention relates to digital processing circuitry and more prticularly to low power circuits for digital processing.
2. Prior Art
Electronic calculator systems of the type having all the main electronic functions within a single, large scaled integrated (LSI) semiconductor chip or small numbers of chips are described in the following prior applications or patents assigned to Texas Instruments Incorporated:
U.S. Pat. No. 3,819,921 by Kilby et al for "Miniature Electronic Calculator", based on an application originally filed Sept. 29, 1967;
U.S. Pat. No. 4,074,351 by Boone and Cochran for "Variable Function Program Calculator";
U.S. Pat. No. 3,819,957 by Bryant for "Digital Mask Logic in Electronic Calculator Chip"; and
U.S. Pat. No. 3,987,416 by Vandierendonct, Fischer and Hartsell for "Electronic Calculator With Display and Keyboard Scanning".
These prior inventions made possible vast reductions in cost and size and increases in functions of electronic calculators. Many millions of such calculators have been produced. The efforts to reduce manufacturing costs and increase the functions available to the user are continuing. Particularly it is desired to provide a basic chip structure that is quite versatile and can be used for many different types of calculators and similar digital processing equipment. This permits a single manufacturing facility to produce a large quantity of the same devices, differing only in a single mask change, to produce a dozen variations while still maintaining large volume cost advantages.
The previous MOS/LSI calculator chips as referred to above were generally register organized in that a single instruction word operated on all of the digits in a given register. A more versatile approach is to make the machine digit organized, operating on one digit at a time. For example, it may be desired to test or set a particular one bit flag. In a register machine, an entire 13 digit register must be addressed and masked to implement this, whereas a digit organized machine may access only the needed digit or bit. An example of such a processing chip is disclosed in U.S. Pat. No. 3,991,305 by Caudel et al entitled, "Electronic Calculator or Digital Processor Chip with Multiple Code Combinations of Display and Keyboard Scan Outputs". This patent discloses what is commonly known in industry as the TMS 1000 architecture for a 4 bit microcomputer. Another approach using this same type of architecture is disclosed in U.S. patent application Ser. No. 216,113 entitled, "Dual Register Digital Processor System" by Koeppen, Rogers, Solimeno and Brown. The architecture disclosed herein is similar to the TMS 1000 architecture, and the architecture disclosed in the above applications is implemented with low power circuitry.
FIG. 1a illustrates a prior art attempt at low power operation using positive channel MOS (P-MOS) field effect transistor devices. This type of circuit is referred to as precharge and conditional discharge circuitry. The node 800 becomes charged during .phi. 3. It should be noted that since the circuitry is presented in P-MOS, the devices are active during the negative portions of the timing signals. This node remains charged until conditionally discharged by the input line during .phi. 1. If the input line remains high, then the node will remain charged and the output will remain at -V as shown in FIG. 1b. However, if the input is low, thus activating device 801, the node 800 will be discharged during .phi. 1 as shown. The disadvantage to this standard percharge/discharge logic is that the precharge period can cause problems in other circuits, such as in addressing RAM cells. If percharge/discharge logic were connected directly in the addressing portion of the RAM cell, all the addresses would be ON during the precharge time. Therefore if precharge/discharge logic were to be used to address a RAM, additional circuitry would be required to buffer the precharge intervals from the addressing lines of the RAM cells.
FIG. 2 illustrates a static inverter which includes a device with the depleted region 802 to provide charge at the node connected to the output line. The static inverter removes the precharge problem; however, the static inverter also consumes a larger amount of d.c. current. The static inverter also requires that the size of the load device be much larger than any of the devices in the precharge/discharge circuitry. This is a disadvantage when fabricating the circuitry on a small silicon chip.
A third approach to the low power circuit operation is shown in FIG. 3, which is a complementary MOS (CMOS) inverter. The clocked CMOS inverter does not have precharges and does not require constant d.c. current. However, the CMOS fabrication process is more expensive and more complex than a normal PMOS or NMOS fabrication process.
The low power approach to many semiconductor display applications has included the use of CMOS, precharge/discharge and static devices. One such application is circuitry required for liquid crystal displays. Liquid crystal displays require low amounts of power and thus interface well with low power processing circuitry. A reference for liquid crystal display requirements is the International Handbook of Liquid Crystal Displays 1975-76, Second Edition, with 1976 Supplement by Martin Tobias, published by Ovum Ltd. 14 Pen Road, London, NC 9RD, England. Another reference is "General Information on Liquid Crystal Display", published by Epson America, Incorporated, 2990 West Lomita Boulevard, Tolerance, Calif. A third reference is an article entitled, "Liquid Crystal Displays" by L. A. Goodman, printed in the Journal of Vacuum Science and Technology, Vol. 10, No. 5, September/October 1973.
In the past, the LCD devices have required the use of low power circuitry such as the precharge discharge logic, or CMOS logic. This specification discloses another alternative, a low power circuit that makes possible a low power interface to LCD's without the disadvantages of the three prior art circuits.